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CMOS Static RAM 64K (64K x 1-Bit)
Description
IDT7187S IDT7187L
x
Features
High speed (equal access and cycle time) - Military: 25/35/45/55/70/85ns (max.) Low power consumption Battery backup operation--2V data retention (L version only) JEDEC standard high-density 22-pin ceramic DIP packaging Produced with advanced CMOS high-performance technology Separate data input and output Input and output directly TTL-compatible Military product compliant to MIL-STD-883, Class B
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The IDT7187 is a 65,536-bit high-speed static RAM organized as 64K x 1. It is fabricated using IDT's high-performance, high-reliability CMOS technology. Access times as fast as 25ns are available. Both the standard (S) and low-power (L) versions of the IDT7187 provide two standby modes--ISB and ISB1. ISB provides low-power operation; ISB1 provides ultra-low-power operation. The low-power (L) version also provides the capability for data retention using battery backup. When using a 2V battery, the circuit typically consumes only 30W. Ease of system design is achieved by the IDT7187 with full asynchronous operation, along with matching access and cycle times. The device is packaged in an industry standard 22-pin, 300 mil ceramic DIP. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
Functional Block Diagram
A A VCC A A A A A CS DATAIN COLUMN I/O DATAOUT ROW SELECT 65,536-BIT MEMORY ARRAY GND
WE A A A A A A A
2986 drw 01
FEBRUARY 2001
1
(c)2000 Integrated Device Technology, Inc. DSC-2986/09
IDT7187S/L CMOS Static RAM 64K (64K x 1-Bit)
Military Temperature Range
Pin Configuration
A0 A1 A2 A3 A4 A5 A6 A7 DATAOUT WE GND
1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12
Absolute Maximum Ratings (1)
Symbol Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value -0.5 to +7.0 -55 to +125 -65 to +135 -65 to +150 1.0 50 Unit V
o o o
D22-1
VCC A15 A14 A13 A12 A11 A10 A9 A8 DATAIN CS
2986 drw 02
VTERM TA TBIAS TSTG PT IOUT
,
C C C
W mA
2986 tbl 03
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DIP Top View
Capacitance (TA = +25C, f = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 8 8 Unit pF pF
2986 tbl 04
Pin Descriptions
Name A0 - A15 CS WE VCC DATAIN DATAOUT GND Description Address Inputs Chip Select Write Enable Power Data Input Data Output Ground
2986 tbl 01
NOTE: 1. This parameter is determined by device characterization, but is not production tested.
Recommended DC Operations Conditions
Symbol VCC GND VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5
(1)
Typ. 5.0 0
____
Max. 5.5 0 6.0 0.8
Unit V V V V
2986 tbl 05
____
Truth Table(1)
Mode Standby Read Write CS H L L WE X H L Output High-Z DOUT High-Z Power Standby Active Active
2986 tbl 02
NOTE: 1. VIL (min.) = -3.0V for pulse width less than 20ns, once per cycle.
Recommended Operating Temperature and Supply Voltage
Grade Military Temperature -55OC to +125OC GND 0V Vcc 5V 10%
2986 tbl 06
NOTE: 1. H = VIH, L = VIL, X = don't care.
2
IDT7187S/L CMOS Static RAM 64K (64K x 1-Bit)
Military Temperature Range
DC Electrical Characteristics
(VCC = 5.0V 10%)
IDT7187S Symbol |ILI| |ILO| VOL Parameter Input Leakage Current Output Leakage Current Output Low Voltage Test Conditions VCC = Max., VIN = GND to VCC VCC = Max., CS = VIH, VOUT = GND to VCC IOL = 10mA, VCC = Min. IOL = 8mA, VCC = Min. VOH Output High Voltage IOH = -4mA, VCC = Min. Min.
____
IDT7187L Min.
____
Max. 10 10 0.5 0.4
____
Max. 5 5 0.5 0.4
____
Unit A A V
____
____
____
____
____
____
2.4
2.4
V
2986 tbl 07
DC Electrical Characteristics(1)
Symbol ICC1 Parameter Operating Power Supply Current CS = VIL, Outputs Open VCC = Max., f = 0(2) Dynamic Operating Current CS = VIL, Outputs Open VCC = Max., f = fMAX(2) Standby Power Supply Current (TTL Level) CS > VIH, Outputs Open VCC = Max., f = fMAX(2) Full Standby Power Supply Current (CMOS Level) CS > VHC, VCC = Max., VIN < VLC or VIN > VHC, f = 0(2) Power S L S L S L S L
(VCC = 5V 10%, VLC = 0.2V, VHC = VCC - 0.2V)
7187S25 7187L25 105 85 130 110 55 50 20 1.5 7187S35 7187L35 105 85 120 100 50 40 20 1.5 7187S45 7187L45 105 85 120 95 50 35 20 1.5 7187S55 7187L55 105 85 120 90 50 30 20 1.5 7187S70 7187L70 105 85 120 90 50 28 20 1.5 7187S85 7187L85 105 85 120 90 50 28 20 1.5
2986 tbl 08
Unit mA
ICC2
mA
ISB
mA
ISB1
mA
NOTES: 1. All values are maximum guaranteed values. 2. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of 1/tRC. f = 0 means no input lines change.
6.42 3
IDT7187S/L CMOS Static RAM 64K (64K x 1-Bit)
Military Temperature Range
Data Retention Characteristics
(L Version Only) (VHC = VCC - 0.2V, VLC = 0.2V)
Typ. (1) VCC @ Symbol VDR ICCDR tCDR tR
(3)
Max. VCC @ 3.0V
____
Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Tim Operation Recovery Time Input Leakage Current
Test Condition
____
Min. 2.0
____
2.0V
____
2.0V
____
3.0V
____
Unit V A ns ns A
2986 tbl 09
10
____
15
____
600
____
900
____
(3)
CS > VHC VIN > VHC or < VLC
0 tRC
(2)
____
____
____
____
IILII(3)
____
____
____
2
2
NOTES: 1. TA = +25C. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed, but not tested.
Low VCC Data Retention Waveform
DATA RETENTION MODE VCC 4.5V tCDR CS VIH VDR 2V VIH
2986 drw 04
4.5V tR
VDR
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 5ns 1.5V 1.5V See Figures 1 and 2
2986 tbl 10
5V 480 DATAOUT 255 30pF*
,
5V 480 DATAOUT 255 5pF*
, 2986 drw 06
2986 drw 05
Figure 1. AC Test Load *Includes scope and jig capacitances
Figure 2. AC Test Load (for tHZ, tLZ, tWZ and tOW)
4
IDT7187S/L CMOS Static RAM 64K (64K x 1-Bit)
Military Temperature Range
AC Electrical Characteristics (VCC = 5.0V 10%)
7187S25 7187L25 Symbol Parameter Min. Max. 7187S35/45 7187L35/45 Min. Max. 7187S55 7187L55 Min. Max. 7187S70 7187L70 Min. Max. 7187S85 7187L85 Min. Max. Unit
Read Cycle
tRC tAA tACS tOH tLZ(1) tHZ(1) tPU tPD
(1) (1)
Read Cycle Time Address Access Time Chip Select Access Time Output Hold from Address Change Output Select to Output in Low-Z Chip Desele ct to Output in High-Z Chip Sele ct to Power Up Time Chip Deselect to Power Down Time
25
____
____
35/45
____
____
55
____
____
70
____
____
85
____
____
ns ns ns ns ns ns ns ns
2986 tbl 11
25 25
____
35/45 35/45
____
55 55
____
70 70
____
85 85
____
____
____
____
____
____
5 5
____
5 5
____
5 5
____
5 5
____
5 5
____
____
____
____
____
____
12
____
17/20
____
30
____
30
____
40
____
0
____
0
____
0
____
0
____
0
____
20
30/35
35
35
40
NOTE: 1. This parameter guaranteed but not tested.
Timing Waveform of Read Cycle No. 1(1,2)
tRC (5) ADDRESS tAA tOH DATAOUT PREVIOUS DATA VALID DATA VALID
2986 drw 07
Timing Waveform of Read Cycle No. 2(1,3)
tRC (5) CS t ACS t LZ (4) DATAOUT tPU VCC SUPPLY CURRENT ICC ISB
2986 drw 08
t HZ(4) DATA VALID tPD
HIGH IMPEDANCE
NOTES: 1. WE is HIGH for Read cycle. 2. CS is LOW for Read cycle. 3. Address valid prior to or coincident with CS transition LOW. 4. Transition is measured 200mV from steady state voltage with specified loading in Figure 2. 5. All Read cycle timings are referenced from the last valid address to the first transitioning address.
6.42 5
IDT7187S/L CMOS Static RAM 64K (64K x 1-Bit)
Military Temperature Range
AC Electrical Characteristics (VCC = 5.0V 10%)
7187S25 7187L25 Symbol Parameter Min. Max. 7187S35/45 7187L35/45 Min. Max. 7187S55 7187L55 Min. Max. 7187S70 7187L70 Min. Max. 7187S85 7187L85 Min. Max. Unit
Write Cycle
tWC tCW tAW tAS tWP tWR tDW tDH tWZ(1) tOW
(1)
Write Cycle Time Chip Select to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Data Hold Time Write Enable to Output in High-Z Output Active from End-of-Write
25 20 20 0 20 0 15 5
____
____
35/45 25/40 25/40 0 20/25 0 15/25 5
____
____
55 50 50 0 35 0 25 5
____
____
70 55 55 0 40 0 30 5
____
____
85 65 65 0 45 0 35 5
____
____
ns ns ns ns ns ns ns ns ns ns
2986 tbl 12
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____ ____
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____ ____
____ ____
____ ____
____ ____
____
____
____
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12
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15/30
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30
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30
____
40
____
0
0
0
0
0
NOTE: 1. This parameter guaranteed but not tested.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,3,4)
t WC ADDRESS tAW CS t AS WE tWZ (5) DATAOUT tDW DATAIN tDH tOW (5) t WP t WR
VALID DATA
2986 drw 09
NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state. 5. Transition is measured 200mV from steady state with a 5pF load (including scope and jig).
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IDT7187S/L CMOS Static RAM 64K (64K x 1-Bit)
Military Temperature Range
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,2,4)
tWC ADDRESS tAW CS t AS WE tDW DATAIN VALID DATA
2986 drw 10
tCW
ttWR(3)
tDH
NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state. 5. Transition is measured 200mV from steady state with a 5pF load (including scope and jig).
Ordering Information
IDT7187 Device Type X Power XX Speed X Package X Process/ Temperature Range
B
Military (-55C to +125C) Compliant to MIL-STD-883, Class B
,
D
300 mil Ceramic DIP (D22-1)
25 35 45 55 70 85
Speed in nanoseconds
S L
Standard Power Low Power
2986 drw 11
6.42 7
IDT7187S/L CMOS Static RAM 64K (64K x 1-Bit)
Military Temperature Range
Datasheet Document History
11/xx/99 Pp. 1, 2, 8 Pp. 3, 4 Pg. 8 08/09/00 02/01/01 Updated to new format Revised package offerings Removed commercial temperature data Added Datasheet Document History Not recommended for new designs Removed "Not recommended for new designs"
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for Tech Support: sramhelp@idt.com 800 544-7726, x4033
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